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four adcs/eight dacs with pll, 192 khz, 24-bit codec ad1937 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features pll-generated clock or direct master clock low emi design 112 db dac/107 db adc dynamic range and snr ?96 db thd + n single 3.3 v supply tolerance for 5 v logic inputs supports 24-bits and 8 khz to 192 khz sample rates differential adc input differential dac output log volume control with autoramp function i 2 c-controllable for flexibility software-controllable clickless mute software power-down right-justified, left-justified, i 2 s, and tdm modes master and slave modes up to 16-channel input/output available in a 64-lead lqfp aecq-100 qualified applications automotive audio systems home theater systems set-top boxes digital audio effects processors general description the ad1937 is a high performance, single-chip codec that provides four analog-to-digital converters (adcs) with differential input and eight digital-to-analog converters (dacs) with differential output, using the analog devices, inc., patented multibit sigma- delta (-) architecture. an i 2 c? port is included, allowing a microcontroller to adjust volume and many other parameters. the ad1937 operates from 3.3 v digital and analog supplies. the ad1937 is available in a 64-lead (differential output) lqfp. the ad1937 is designed for low emi. this consideration is apparent in both the system and circuit design architectures. by using the on-board pll to derive the master clock from the lr (frame) clock or from an external crystal, the ad1937 elimi- nates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. the dacs and adcs are designed using the latest analog devices continuous time architecture to further minimize emi. by using 3.3 v supplies, power consumption is minimized and further reduces emissions. functional block diagram digital filter serial data port digital audio input/output precision voltage reference timing management and control (clock and pll) i 2 c control port control data input/output ad1937 adc adc adc adc a nalog audio inputs analog audio outputs dac dac dac dac dac dac dac dac digital filter and volume control sdata out sdata in clocks 07414-001 figure 1.
ad1937 rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 test conditions ............................................................................. 3 analog performance specifications ........................................... 3 crystal oscillator specifications................................................. 5 digital specifications ................................................................... 6 power supply specifications........................................................ 6 digital filters ................................................................................. 7 timing specifications .................................................................. 8 timing diagrams .......................................................................... 9 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 13 theory of operation ...................................................................... 15 analog-to-digital converters (adcs) .................................... 15 digital-to-analog converters (dacs) .................................... 15 clock signals ............................................................................... 15 reset and power-down ............................................................. 16 i 2 c control port .......................................................................... 16 power supply and voltage reference ....................................... 18 serial data portsdata format ............................................... 19 time-division multiplexed (tdm) modes ............................ 20 daisy-chain mode ..................................................................... 23 additional modes ....................................................................... 26 control registers ............................................................................ 27 definitions ................................................................................... 27 pll and clock control registers ............................................. 27 dac control registers .............................................................. 28 adc control registers .............................................................. 30 applications circuits ...................................................................... 32 outline dimensions ....................................................................... 33 ordering guide .......................................................................... 33 revision history 9/08revision 0: initial version
ad1937 rev. 0 | page 3 of 36 specifications test conditions performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specific ations. table 1. parameter value supply voltages (avdd, dvdd) 3.3 v temperature as specified in table 2 and table 3 master clock 12.288 mhz (48 khz f s , 256 f s mode) input sample rate 48 khz measurement bandwidth 20 hz to 20 khz word width 24 bits load capacitance (digital output) 20 pf load current (digital output) 1 ma or 1.5 k to ? dvdd supply input voltage high 2.0 v input voltage low 0.8 v analog performance specifications specifications guaranteed at a t a of 25c. table 2. parameter conditions/comments min typ max unit analog-to-digital converters adc resolution all adcs 24 bits dynamic range 20 hz to 20 khz, ?60 db input no filter (rms) 96 102 db with a-weighted filter (rms) 98 105 db total harmonic distortion + noise ?1 dbfs ?96 ?87 db full-scale input voltage (differential) 1.9 v rms gain error ?10 +10 % interchannel gain mismatch ?0.25 +0.25 db offset error ?10 0 +10 mv gain drift 100 ppm/c interchannel isolation ?110 db cmrr 100 mv rms, 1 khz 55 db 100 mv rms, 20 khz 55 db input resistance 14 k input capacitance 10 pf input common-mode bias voltage 1.5 v digital-to-analog converters dac resolution all dacs 24 bits dynamic range 20 hz to 20 khz, ?60 db input no filter (rms) 102 107 db with a-weighted filter (rms) 105 110 db with a-weighted filter (average) 112 db
ad1937 rev. 0 | page 4 of 36 parameter conditions/comments min typ max unit total harmonic distortion + noise 0 dbfs two channels running ?94 db eight channels running ?86 ?76 db full-scale output voltage 1.76 (4.96) v rms (v p-p) gain error ?10 +10 % interchannel gain mismatch ?0.2 +0.2 db offset error ?25 ?6 +25 mv gain drift ?30 +30 ppm/c interchannel isolation 100 db interchannel phase deviation 0 degrees volume control step 0.375 db volume control range 95 db de-emphasis gain error 0.6 db output resistance at each pin 100 reference internal reference voltage filtr pin 1.50 v external reference voltage filtr pin 1.32 1.50 1.68 v common-mode reference output cm pin 1.50 v regulator input supply voltage vsupply pin 4.5 5 5.5 v regulated output voltage vsense pin 3.19 3.37 3.55 v
ad1937 rev. 0 | page 5 of 36 specifications measured at a t c of 130c. table 3. parameter conditions/comments min typ max unit analog-to-digital converters adc resolution all adcs 24 bits dynamic range 20 hz to 20 khz, ?60 db input no filter (rms) 93 102 db with a-weighted filter (rms) 96 104 db total harmonic distortion + noise ?1 dbfs ?96 ?87 db full-scale input voltage (differential) 1.9 v rms gain error ?10 +10 % interchannel gain mismatch ?0.25 +0.25 db offset error ?10 0 +10 mv digital-to-analog converters dac resolution all dacs 24 bits dynamic range 20 hz to 20 khz, ?60 db input no filter (rms) 101 107 db with a-weighted filter (rms) 104 110 db with a-weighted filter (average) 112 db total harmonic distortion + noise 0 dbfs two channels running ?94 db eight channels running ?86 ?70 db full-scale output voltage 1.76 (4.96) v rms (v p-p) gain error ?10 +10 % interchannel gain mismatch ?0.2 +0.2 db offset error ?25 ?6 +25 mv gain drift ?30 +30 ppm/c reference internal reference voltage filtr pin 1.50 v external reference voltage filtr pin 1.32 1.50 1.68 v common-mode reference output cm pin 1.50 v regulator input supply voltage vsupply pin 4.5 5 5.5 v regulated output voltage vsense pin 3.2 3.43 3.65 v crystal oscillator specifications table 4. parameter min typ max unit transconductance 3.5 mmhos
ad1937 rev. 0 | page 6 of 36 digital specifications ?40c < t a < +130c, dvdd = 3.3 v 10%. table 5. parameter conditions/comments min typ max unit input high level input voltage (v ih ) 2.0 v mclki/mclkxi pin 2.2 v low level input voltage (v il ) 0.8 v input leakage i ih @ v ih = 2.4 v 10 a i il @ v il = 0.8 v 10 a input capacitance 5 pf output high level output voltage (v oh ) i oh = 1 ma dvdd ? 0.60 v low level output voltage (v ol ) i ol = 1 ma 0.4 v power supply specifications table 6. parameter conditions/comments min typ max unit supplies voltage dvdd 3.0 3.3 3.6 v avdd 3.0 3.3 3.6 v vsupply 4.5 5.0 5.5 v digital current master clock = 256 f s normal operation f s = 48 khz 56 ma f s = 96 khz 65 ma f s = 192 khz 95 ma power-down f s = 48 khz to 192 khz 2.0 ma analog current normal operation 74 ma power-down 23 ma dissipation operation master clock = 256 f s , 48 khz all supplies 429 mw digital supply 185 mw analog supply 244 mw power-down, all supplies 83 mw power supply rejection ratio signal at analog supply pins 1 khz, 200 mv p-p 50 db 20 khz, 200 mv p-p 50 db
ad1937 rev. 0 | page 7 of 36 digital filters table 7. parameter mode factor min typ max unit adc decimation filter all modes, typical @ 48 khz pass band 0.4375 f s 21 khz pass-band ripple 0.015 db transition band 0.5 f s 24 khz stop band 0.5625 f s 27 khz stop-band attenuation 79 db group delay 22.9844 f s 479 s dac interpolation filter pass band 48 khz mode, typical @ 48 khz 0.4535 f s 22 khz 96 khz mode, typical @ 96 khz 0.3646 f s 35 khz 192 khz mode, typical @ 192 khz 0.3646 f s 70 khz pass-band ripple 48 khz mode, typical @ 48 khz 0.01 db 96 khz mode, typical @ 96 khz 0.05 db 192 khz mode, typical @ 192 khz 0.1 db transition band 48 khz mode, typical @ 48 khz 0.5 f s 24 khz 96 khz mode, typical @ 96 khz 0.5 f s 48 khz 192 khz mode, typical @ 192 khz 0.5 f s 96 khz stop band 48 khz mode, typical @ 48 khz 0.5465 f s 26 khz 96 khz mode, typical @ 96 khz 0.6354 f s 61 khz 192 khz mode, typical @ 192 khz 0.6354 f s 122 khz stop-band attenuation 48 khz mode, typical @ 48 khz 70 db 96 khz mode, typical @ 96 khz 70 db 192 khz mode, typical @ 192 khz 70 db group delay 48 khz mode, typical @ 48 khz 25 f s 521 s 96 khz mode, typical @ 96 khz 11 f s 115 s 192 khz mode, typical @ 192 khz 8 f s 42 s
ad1937 rev. 0 | page 8 of 36 timing specifications ?40c < t a < +130c, dvdd = 3.3 v 10%. table 8. parameter condition comments min max unit input master clock (mclk) and reset t mh mclk duty cycle dac/adc clock source = pll clock @ 256 f s , 384 f s , 512 f s , and 768 f s 40 60 % t mh dac/adc clock source = direct mclk @ 512 f s (bypass on-chip pll) 40 60 % f mclk mclk frequency pll mode, 256 f s reference 6.9 13.8 mhz f mclk direct 512 f s mode 27.6 mhz t pdr low 15 ns t pdrr recovery reset to active output 4096 t mclk pll lock time mclk or lrclk 10 ms 256 f s vco clock, output duty cycle, mclko/mclkxo pin 40 60 % i 2 c see figure 13 and figure 14 f scl scl clock frequency 400 khz t scll scl low 1.3 s t sclh scl high 0.6 s t scs setup time (start condition) relevent for repeated start condition 0.6 s t sch hold time (start condition) first clock generated after this period 0.6 s t ssh setup time (stop condition) 0.6 s t ds data setup time 100 ns t sr sda and scl rise time 300 ns t sf sda and scl fall time 300 ns t bft bus-free time between stop and start 1.3 s dac serial port see figure 2 t dbh dbclk high slave mode 10 ns t dbl dbclk low slave mode 10 ns t dls dlrclk setup to dbclk rising, slave mode 10 ns dlrclk skew from dbclk falling, master mode ?8 +8 ns t dlh dlrclk hold from dbclk rising, slave mode 5 ns t dds dsdata setup to dbclk rising 10 ns t ddh dsdata hold from dbclk rising 5 ns adc serial port see figure 3 t abh abclk high slave mode 10 ns t abl abclk low slave mode 10 ns t als alrclk setup to abclk rising, slave mode 10 ns alrclk skew from abclk falling, master mode ?8 +8 ns t alh alrclk hold from abclk rising, slave mode 5 ns t abdd asdata delay from abclk falling, any mode 18 ns auxiliary interface t axds aauxdata setup to auxbclk rising 10 ns t axdh aauxdata hold from auxbclk rising 5 ns t dxdd dauxdata delay from auxbclk falling 18 ns t xbh auxbclk high 10 ns t xbl auxbclk low 10 ns t dls auxlrclk setup to auxbclk rising 10 ns t dlh auxlrclk hold from auxbclk rising 5 ns
ad1937 rev. 0 | page 9 of 36 timing diagrams dbclk dlrclk dsdatax left-justified mode dsdatax right-justified mode dsdatax i 2 s-justified mode t dlh t dbh t dbl t dls t dds msb msb msb lsb msb ? 1 t ddh t dds t ddh t dds t ddh t ddh t dds 07414-025 figure 2. dac serial timing abclk alrclk asdatax left-justified mode asdatax right-justified mode asdatax i 2 s-justified mode t abh lsb msb msb msb msb ? 1 t abl t als t abdd t abdd t abdd t alh 0 7414-026 figure 3. adc serial timing
ad1937 rev. 0 | page 10 of 36 absolute maximum ratings thermal resistance table 9. parameter rating analog (avdd) ?0.3 v to +3.6 v digital (dvdd) ?0.3 v to +3.6 v vsupply ?0.3 v to +6.0 v input current (except supply pins) 20 ma analog input voltage (signal pins) C0.3 v to avdd + 0.3 v digital input voltage (signal pins) ?0.3 v to dvdd + 0.3 v operating temperature range (case) ?40c to +125c storage temperature range ?65c to +150c ja represents junction-to-ambient thermal resistance; jc represents the junction-to-case thermal resistance. all characteristics are for a 4-layer board. table 10. package type ja jc unit 64-lead lqfp 47 11.1 c/w esd caution stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ad1937 rev. 0 | page 11 of 36 pin configuration and fu nction descriptions nc = no connect nc 64 nc 63 avdd 62 lf 61 adc2rn 60 adc2rp 59 adc2ln 58 adc2lp 57 adc1rn 56 adc1rp 55 adc1ln 54 adc1lp 53 cm 52 avdd 51 nc 50 nc 49 dvdd 17 dsdata3 18 dsdata2 19 dsdata1 20 dbclk 21 dlrclk 22 vsupply 23 vsense 24 vdrive 25 asdata2 26 asdata1 27 abclk 28 alrclk 29 addr0 30 sda 31 dvdd 32 agnd 1 mclki/mclkxi 2 mclko/mclkxo 3 agnd 4 avdd 5 dac3lp 6 dac3ln 7 dac3rp 8 dac3rn 9 dac4lp 10 dac4ln 11 dac4rp 12 dac4rn 13 pd/rst 14 dsdata4 15 dgnd 16 agnd 48 filtr 47 agnd 46 avdd 45 agnd 44 dac2rn 43 dac2rp 42 dac2ln 41 dac2lp 40 dac1rn 39 dac1rp 38 dac1lp 36 addr1 35 scl 34 dgnd 33 dac1ln 37 ad1937 top view (not to scale) differential output 07414-002 figure 4. pin configuration table 11. pin function descriptions pin no. type 1 mnemonic description 1, 4, 44, 46, 48 i agnd analog ground. 2 i mclki/mclkxi master clock input/crystal oscillator input. 3 o mclko/mclkxo master clock output/crystal oscillator output. 5, 45, 51, 62 i avdd analog power supply. connect this pin to analog 3.3 v supply. 6 o dac3lp dac3 left positive output. 7 o dac3ln dac3 left negative output. 8 o dac3rp dac3 right positive output. 9 o dac3rn dac3 right negative output. 10 o dac4lp dac4 left positive output. 11 o dac4ln dac4 left negative output. 12 o dac4rp dac4 right positive output. 13 o dac4rn dac4 right negative output 14 i pd / rst power-down reset (active low). 15 i/o dsdata4 dac serial data input 4. data input to dac4 data in/tdm dac2 data out (dual-line mode)/ aux dac2 data out (to external dac2). 16, 33 i dgnd digital ground. 17, 32 i dvdd digital power supply. connect this pin to digital 3.3 v supply. 18 i/o dsdata3 dac serial data input 3. data input to dac3 data in/tdm dac2 data in (dual-line mode)/aux adc2 data in (from external adc2). 19 i/o dsdata2 dac serial data input 2. data input to dac2 data in/tdm dac data out/aux adc1 data in (from external adc1). 20 i dsdata1 dac serial data input 1. data input to dac1 data in/tdm dac data in/tdm data in. 21 i/o dbclk bit clock for dacs. can be prog rammed as input or output in all modes. 22 i/o dlrclk frame clock for dacs. can be pr ogrammed as input or output in all modes.
ad1937 rev. 0 | page 12 of 36 pin no. type 1 mnemonic description 23 i vsupply 5 v input to regulator, emitter of pass transistor. 24 i vsense connect 3.3 v regulator output, collector of pass transistor, to this pin. 25 o vdrive drive for base of pass transistor. 26 i/o asdata2 adc serial data output 2. data output from adc2/tdm adc data in/aux dac1 data out (to external dac1). 27 o asdata1 adc serial data output 1. data output from adc1/tdm adc data out/tdm data out. 28 i/o abclk bit clock for adcs. can be prog rammed as input or output in all modes. 29 i/o alrclk frame clock for adcs. can be pr ogrammed as input or output in all modes. 30 i addr0 i 2 c address assignment. 31 i/o sda control data port (i 2 c). 34 i scl control clock port (i 2 c). 35 i addr1 i 2 c address assignment. 36 o dac1lp dac1 left positive output. 37 o dac1ln dac1 left negative output. 38 o dac1rp dac1 right positive output. 39 o dac1rn dac1 right negative output. 40 o dac2lp dac2 left positive output. 41 o dac2ln dac2 left negative output. 42 o dac2rp dac2 right positive output. 43 o dac2rn dac2 right negative output. 47 o filtr analog voltage reference filter capacitor connection. bypass with 10 f||100 nf to agnd. 49, 50, 63, 64 nc no connect. 52 o cm common-mode reference filter capacitor connection. bypass with 47 f||100 nf to agnd. 53 i adc1lp adc1 left positive input. 54 i adc1ln adc1 left negative input. 55 i adc1rp adc1 right positive input. 56 i adc1rn adc1 right negative input. 57 i adc2lp adc2 left positive input. 58 i adc2ln adc2 left negative input. 59 i adc2rp adc2 right positive input. 60 i adc2rn adc2 right negative input. 61 o lf pll loop filter, return to avdd. 1 i = input, o = output.
ad1937 rev. 0 | page 13 of 36 8 typical performance characteristics 0.10 0.08 0.06 0.04 0.02 0 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 01 16141210 8642 magnitude (db) frequency (khz) 07414-003 figure 5. adc pass-band filter response, 48 khz 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 04 5 101520253035 magnitude (db) frequency (khz) 0 07414-004 figure 6. adc stop-band filter response, 48 khz 0.06 0.04 0.02 ?0.06 ?0.04 ?0.02 0 02 16 8 magnitude (db) frequency (khz) 4 07414-005 figure 7. dac pass-band filter response, 48 khz 0 ?150 ?100 ?50 04 12 24 36 magnitude (db) frequency (khz) 8 07414-006 figure 8. dac stop-band filter response, 48 khz 0.10 ?0.10 ?0.05 0 0.05 09 72 48 24 magnitude (db) frequency (khz) 6 07414-007 figure 9. dac pass-band filter response, 96 khz 0 ?150 ?100 ?50 09 24 48 72 magnitude (db) frequency (khz) 6 07414-008 figure 10. dac stop-band filter response, 96 khz
ad1937 rev. 0 | page 14 of 36 4 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 06 81 63 2 magnitude (db) frequency (khz) 07414-009 figure 11. dac pass-band filter response, 192 khz ?10 ?8 ?6 ?4 ?2 0 48 96 64 80 magnitude (db) frequency (khz) 07414-010 figure 12. dac stop-band filter response, 192 khz
ad1937 rev. 0 | page 15 of 36 theory of operation analog-to-digital converters (adcs) there are four adc channels in the ad1937 configured as two stereo pairs with differential inputs. the adcs can operate at a nominal sample rate of 48 khz, 96 khz, or 192 khz. the adcs include on-board digital antialiasing filters with 79 db stop- band attenuation and linear phase response, operating at an oversampling ratio of 128 (48 kh z, 96 khz, and 192 khz modes). digital outputs are supplied through two serial data output pins (one for each stereo pair): a common frame clock (alrclk) and a common bit clock (abclk). alternatively, the tdm modes can be used to access up to 16 channels on a single tdm data line. the adcs must be driven from a differential signal source for best performance. the input pins of the adcs connect to internal switched capacitors. to isolate the external driving op amp from the glitches caused by the internal switched capacitors, each input pin should be isolated by using a series-connected external 100 resistor and a 1 nf capacitor connected from each input to ground. use a high quality capacitor such as a ceramic np0/c0g, or polypropylene film. the differential inputs have a nominal common-mode voltage of 1.5 v. the voltage at the common-mode reference pin (cm) can be used to bias external op amps to buffer the input signals (see the power supply and voltage reference section). the inputs can also be ac-coupled and in that case do not need an external dc bias to cm. a digital high-pass filter can be switched in line with the adcs (adc control 0 register) to remove residual dc offsets. it has a 1.4 hz, 6 db per octave cutoff at a 48 khz sample rate. the cutoff frequency scales directly with sample frequency. digital-to-analog converters (dacs) the ad1937 dac channels are arranged in four stereo pairs, giving eight analog outputs; the outputs are differential for improved noise and distortion performance. the dacs include on-board digital reconstruction filters with 70 db stop-band attenuation and linear phase response, operating at an over- sampling ratio of 4 (48 khz or 96 khz modes) or 2 (192 khz mode). each channel has its own independently programmable attenuator, adjustable in 255 steps in increments of 0.375 db. digital inputs are supplied through four serial data input pins (one for each stereo pair), a common frame clock (dlrclk), and a common bit clock (dbclk). alternatively, one of the tdm modes can be used to access up to 16 channels on a single tdm data line. each output pin has a nominal common-mode dc level of 1.5 v and swings 1.27 v for a 0 dbfs digital input signal. a single op amp, third-order, external, low-pass filter is recommended to remove high frequency noise present on the output pins, as well as to provide a differential-to-single-ended conversion for the differential output. note that the use of op amps with low slew rates or low bandwidth can cause high frequency noise and tones to fold down into the audio band; exercise care in selecting these components. the voltage at cm can be used to bias the external op amps that buffer the output signals (see the power supply and voltage reference section). clock signals the on-chip phase-locked loop (pll) can be selected to ref- erence the input sample rate from either of the lrclk pins or 256, 384, 512, or 768 sample rate s (f s ), referenced to the 48 khz mode from the mclki/mclkxi pin. the default at power-up is 256 f s from the mclki/mclkxi pin. in 96 khz mode, the master clock frequency stays at the same absolute frequency; therefore, the actual multiplication rate is divided by 2. in 192 khz mode, the actual multiplication rate is divided by 4. for example, if the ad1937 is programmed in 256 f s mode, the frequency of the master clock input is 256 48 khz = 12.288 mhz. if the ad1937 is then switched to 96 khz operation (by writing to the i 2 c port), the frequency of the master clock should remain at 12.288 mhz, which is 128 f s in this example. in 192 khz mode, this becomes 64 f s . the internal clock for the adcs is 256 f s for all clock modes. the internal clock for the dacs varies by mode: 512 f s (48 khz mode), 256 f s (96 khz mode), or 128 f s (192 khz mode). by default, the on-board pll generates this internal master clock from an external clock. a direct 512 f s (referenced to 48 khz mode) master clock can be used for either the adcs or dacs, if selected in the pll and clock control 1 register. note that it is not possible to use a direct clock for the adcs set to the 192 khz mode. it is required that the on-chip pll be used in this mode. the pll can be powered down in the pll and clock control 0 register. to ensure reliable locking when changing pll modes, or if the reference clock is unstable at power-on, power down the pll and then power it back up after the reference clock has stabilized. the internal master clock (mclk) can be disabled in the pll and clock control 0 register to reduce power dissipation when the ad1937 is idle. the clock should be stable before it is enabled. unless a standalone mode is selected (see the i 2 c control port section), the clock is disabled by reset and must be enabled by writing to the i 2 c port for normal operation.
ad1937 rev. 0 | page 16 of 36 to maintain the highest performance possible, limit the clock jitter of the internal master clock signal to less than a 300 ps rms time interval error (tie). even at these levels, extra noise or tones can appear in the dac outputs if the jitter spectrum contains large spectral peaks. if the internal pll is not used, it is best to use an independent crystal oscillator to generate the master clock. in addition, it is especially important that the clock signal not pass through an fpga, cpld, or other large digital chip (such as a dsp) before being applied to the ad1937. in most cases, this induces clock jitter due to the sharing of common power and ground connections with other unrelated digital output signals. when the pll is used, jitter in the reference clock is attenuated above a certain frequency depending on the loop filter. reset and power-down the function of the pd / rst pin sets all the control registers to their default settings. to avoid audio pops, pd / rst does not power down the analog outputs. after pd / rst is deasserted and the pll acquires lock condition, an initialization routine runs inside the ad1937. this initialization lasts for approx- imately 256 master clock cycles. once the routine is complete, the registers can be programmed. the power-down bits in the pll and clock control 0, dac control 1, and adc control 1 registers power down their respective sections. all other register settings are retained. to guarantee proper startup, the pd / rst pin should be pulled low by an external resistor. i 2 c control port the ad1937 has an i 2 c-compatible control port that permits programming and reading back the internal control registers for the adcs, dacs, and clock system. there is also a stand- alone mode available for operation without serial control, configured at reset using the serial control pins. all registers are set to default except internal mclk enable, which is set to 1 and adc bclk and lrclk master/slave is set by sda (see table 12 for details). table 12. hardware selection of standalone mode adc clocks addr0 (pin 30) sda (pin 31) scl (pin 34) addr1 (pin 35) slave 0 0 0 0 master 0 1 0 0 the i 2 c interface of the ad1937 is a 2-wire interface that consists of a clock line (scl) and a data line (sda). sda is bidirectional and the ad1937 drives sda either to acknowl- edge the master (ack) or to send data during a read operation. the sda pin for the i 2 c port is an open-drain collector and requires a 2 k pull-up resistor. a write or read access occurs when the sda line is pulled low while the scl line is high, indicated by start in the timing diagrams. sda is only allowed to change when scl is low except when a start or stop condition occurs, as shown in figure 13 and figure 14 . the first eight bits of the data-word consist of the device address and the r/ w bit. the device address consists of an internal built-in address (0x08) ored with the two address bits, addr1 and addr0, and the r/ w bit. the two address bits allow four ad1937s to be used in a system. tie i 2 c addr0 and addr1 low or high and program the addr bits accordingly as 0 or 1. initiating a write operation to the ad1937 involves sending a start condition and then sending the device address with the r/ w bit set low. the ad1937 responds by issuing an acknowledge to indicate that it has been addressed. the user then sends a second frame telling the ad1937 which register is required to be written to. another acknowledge is issued by the ad1937. finally, the user can send another frame with the eight data bits required to be written to the register. a third acknowledge is issued by the ad1937 after which the user can send a stop condition to complete the data transfer. a read operation requires that the user first write to the ad1937 to point to the correct register and then read the data. this is achieved by sending a start condition followed by the device address frame, with the r/ w bit low; the ad1937 returns an acknowledge. the master then sends the register address frame. following the acknowledge from the ad1937, the user must issue a repeated start condition. the next frame is the device address with the r/ w bit set high; the ad1937 returns an acknowledge. on the next frame, the ad1937 outputs the register data on the sda line; the master should send an acknowledge. a stop condition completes the read operation. and show examples of writing to and reading from the dac1l volume control register, address 0x06 (see ). figure 13 figure 14 table 28
ad1937 rev. 0 | page 17 of 36 07414-011 ack. by master (am) stop by master (p) sck (continued) d7 d6 d5 d4 d3 d2 d1 d0 sda (continued) frame 3 data byte to ad1937 s c k s d a start by master (s) ack. by ad1937 (as) ack. by master (am) 00001 addr1 addr0 r/w 0 00 00 0 11 frame 1 chip address byte frame 2 register address byte figure 13. i 2 c write format 07414-012 d7 d6 d5 d4 d3 d2 d1 d0 sda (continued) scl (continued) sck sda start by master (s) ack. by ad1937 (as) ack. by ad1937 (as) 00001 addr1 addr0 r/w 0 00 00 0 11 frame 1 chip address byte frame 2 register address byte repeated start by master (s) ack. by ad1937 (as) ack. by master (am) stop by master (p) frame 3 chip address byte frame 4 register data 0 000 1 addr1 addr0 r/w figure 14. i 2 c read format
ad1937 rev. 0 | page 18 of 36 table 13. i 2 c abbreviation table abbreviation condition s repeated start by master p stop by master am acknowledge by master as acknowledge by ad1937 table 14. single word i 2 c write s chip address, r/ w = 0 as register address as data word as p table 15. burst mode i 2 c write s chip address, r/ w = 0 as register address as data word 1 as data word 2 as data word n as p table 16. single word i 2 c read s chip address, r/ w = 0 as register address as s chip address, r/ w = 1 as data word am p table 17. burst mode i 2 c read s chip address, r/ w = 0 as register address as s chip address, r/ w = 1 as data word 1 am data word 2 am data word n am p power supply and voltage reference the ad1937 is designed for a 3.3 v supply. separate power supply pins are provided for the analog and digital sections. to minimize noise pickup, these pins should be bypassed with 100 nf ceramic chip capacitors placed as close to the pins as possible. a bulk aluminum electrolytic capacitor of at least 22 f should also be provided on the same printed circuit board (pcb) as the codec. for critical applications, improved performance is obtained with separate supplies for the analog and digital sections. if this is not possible, it is recommended that the analog and digital load pins be isolated by means of a ferrite bead in series with the supply. it is important that the analog supply be as clean as possible. the ad1937 includes a 3.3 v regulator driver that only requires an external pass transistor, a resistor, and bypass capacitors to turn a 5 v supply into 3.3 v. if the regulator driver is not used, connect vsupply, vdrive, and vsense to dgnd. all digital inputs are compatible with ttl and cmos levels. all outputs are driven from the 3.3 v dvdd supply and are compatible with ttl and 3.3 v cmos levels. the adc and dac internal analog voltage reference (v ref ) is brought out on the filtr pin and should be bypassed as close as possible to the chip with a parallel combination of 10 f and 100 nf capacitors. any external current drawn should be limited to less than 50 a. the internal reference can be disabled in the pll and clock control 1 register, and filtr can be driven from an external source. this can be used to scale the dac output to the clipping level of a power amplifier based on its power supply voltage. the adc input gain varies by the inverse ratio. it is not advisable to drive the filtr pin with more than (avdd/2) v. the total gain from adc input to dac output remains constant. the cm pin should be bypassed as close as possible to the chip, with a parallel combination of 47 f and 100 nf capacitors. this voltage can be used to bias external op amps to the common-mode voltage of the input and output signal pins. the output current should be limited to less than 0.5 ma source and 2 ma sink.
ad1937 rev. 0 | page 19 of 36 serial data portsdata format the eight dac channels use a common serial bit clock (dbclk) and a common left-right framing clock (dlrclk) in the serial data port. the four adc channels use a common serial bit clock (abclk) and left-right framing clock (alrclk) in the serial data port. the clock signals are all synchronous with the sample rate. the normal stereo serial modes are shown in figure 15 . the adc and dac serial data modes default to i 2 s stereo. the ports can also be programmed for left-justified stereo, right-justified stereo, and tdm modes. the word width is 24 bits by default and can be set to 16 or 20 bits in the dac control 2 and adc control 1 registers. the dac serial formats are programmable in the dac control 0 register. the polarity of dbclk and dlrclk is programmable in the dac control 1 reg- ister. the adc serial format is programmable in adc control 1 register. the abclk and alrclk clock polarities are pro- grammed in adc control 2 register. in figure 2 , figure 3 , and figure 15 all of the clocks are shown with their normal polarity. both dac and adc serial ports can be programmed to become the bus masters according to dac control 1 and adc control 2 registers. by default, both adc and dac serial ports are in the slave mode. lrclk bclk sdat a lrclk bclk sdat a lrclk bclk sdat a lsb lsb lsb lsb lsb lsb left channel right channel right channel left channel left channel right channel msb msb msb msb msb msb right-justified mode?select number of bits per channel dsp mode?16 bits to 24 bits per channel i 2 s-justified mode?16 bits to 24 bits per channel left-justified mode?16 bits to 24 bits per channel lrclk bclk sdat a lsb lsb notes 1. dsp mode does not identify channel. 2. lrclk normally operates at f s except for dsp mode, which is 2 f s . 3. bclk frequency is normally 64 lrclk but may be operated in burst mode. msb msb 1/ f s 07414-024 figure 15. stereo modes
ad1937 rev. 0 | page 20 of 36 time-division multiplexed (tdm) modes the serial ports of the ad1937 have several different tdm serial data modes. single-line tdm mode is the most com- monly used configuration (see figure 16 and figure 17 ). these figures show 8-channel configuration; other possible options are 4- and 16-channel configurations. in figure 16 , the eight on-chip dac data slots are packed into one i 2 s tdm stream. in this mode, both dbclk and abclk are 256 f s . in figure 17 , the adc serial port outputs one data stream consisting of four on-chip adcs followed by four unused slots. slot 1 left 1 slot 2 right 1 slot 3 left 2 slot 4 right 2 msb msb ? 1 msb ? 2 data bclk lrclk slot 5 left 3 slot 6 right 3 slot 7 left 4 slot 8 right 4 dlrclk dbclk dsdata 256 bclks 32 bclks 07414-014 figure 16. single-line tdm mode 8-channel dac configuration slot 1 left 1 slot 2 right 1 slot 3 left 2 slot 4 right 2 msb msb ? 1 msb ? 2 data bclk lrclk slot 5 slot 6 slot 7 slot 8 alrclk abclk a sdat a 256 bclks 32 bclks 07414-013 figure 17. single-line tdm mode 8-channel adc configuration the i/o pin functions of the serial ports are defined according to the serial mode that is selected. for a detailed description of the function of each pin in tdm and tdm/aux modes, see table 18 . the ad1937 allows systems with more than eight dac channels to be easily configured by the use of an auxiliary serial data port. the tdm/aux mode 16-channel configuration is shown in figure 18 . in this mode, the aux channels are the last four slots of the tdm data stream. these slots are extracted and output to the aux serial port. it should be noted that due to the high dbclk frequency, this mode is available only in the 48 khz/44.1 khz/32 khz sample rates. an 8-channel dac configuration cannot be tdm/aux because there are no extra data slots for the aux packets; this would be single- line tdm mode. the ad1937 also allows system configurations with more than four adc channels as shown in figure 19 (using 8 adcs) and figure 20 (using 16 adcs). due to the high abclk frequency, this mode is available only in the 48 khz/44.1 khz/ 32 khz sample rates. combining the tdm/aux adc and dac modes results in a system configuration of 8 adcs and 12 dacs. the system, then consists of two external stereo adcs, two external stereo dacs, and one ad1937. this mode is shown in figure 21 (combined tdm/aux dac and adc modes). in the tdm/aux mode, the frame sync (alrclk) triggers the tdm word by crossing the high frequency tdm bclk (abclk) to 0, similar to the single-line tdm modes (see figure 16 and figure 17 ). the aux lrclk (dlrclk) runs at the much slower f s of the aux port; the aux bclk (dbclk) runs at 64 f s . this is shown in the tdm/aux figures (see figure 18 to figure 21 ). table 18. pin function changes in tdm and tdm/aux modes mnemonic stereo modes tdm modes tdm/aux modes asdata1 adc1 data out tdm adc data out tdm data out asdata2 adc2 data out tdm adc data in aux dac1 data out (to external dac1) dsdata1 dac1 data in tdm dac data in tdm data in dsdata2 dac2 data in tdm dac data out aux adc1 data in (from external adc1) dsdata3 dac3 data in tdm dac2 data in (dual-line mode) aux adc2 data in (from external adc2) dsdata4 dac4 data in tdm dac2 data out (dual-line mode) aux dac2 data out (to external dac2) alrclk adc lrclk in/out tdm adc frame sync in/out tdm frame sync in/out abclk adc bclk in/out tdm adc bclk in/out tdm bclk in/out dlrclk dac lrclk in/out tdm dac frame sync in/out aux lrclk in/out dbclk dac bclk in/out tdm dac bclk in/out aux bclk in/out
ad1937 rev. 0 | page 21 of 36 left right msb msb msb msb alrclk abclk dsdata1 (tdm data in) dlrclk (aux lrclk in/out) dbclk (aux bclk in/out) asdata2 (aux dac1 data out) dsdata4 (aux dac2 data out) msb empty empty empty empty dac1l dac1r dac2l dac2r dac3l dac3r dac4l dac4r aux1l aux1r aux2l aux2r 8 on-chip dac channels aux dac channels appear at aux dac ports unused slots 32 bits 0 7414-015 figure 18. tdm/aux mode 16-channel dac configuration alrclk abclk dsdata1 (tdm data in) asdata1 (tdm data out) dlrclk (aux lrclk in/out) dbclk (aux bclk in/out) dsdata2 (aux adc1 data in) dsdata3 (aux adc2 data in) dacl1 dacr1 dacl2 dacr2 dacl3 dacr3 dacl4 dacr4 adcl1 adcr1 adcl2 adcr2 auxl1 auxr1 auxl2 auxr2 8 on-chip dac channels 4 on-chip adc channels 4 aux adc channels 32 bits left right msb msb msb msb msb 0 7414-016 figure 19. tdm/aux mode 8-channel adc configuration
ad1937 rev. 0 | page 22 of 36 left right msb msb msb msb dlrclk (aux lrclk in/out) dbclk (aux bclk in/out) dsdata2 (aux adc1 data in) dsdata3 (aux adc2 data in) alrclk abclk asdata1 (tdm data out) msb adcl1 adcr1 adcl2 adcr2 auxl1 auxr1 auxl2 auxr2 unused unused unused unused unused unused unused unused 4 on-chip adc channels auxiliary adc channels unused slots 32 bits 07414-017 figure 20. tdm/aux mode 16-channel adc configuration left right dlrclk (aux lrclk in/out) dbclk (aux bclk in/out) msb msb dsdata2 (aux adc1 data in) msb msb dsdata3 (aux adc2 data in) msb msb asdata2 (aux adc1 data out) msb msb dsdata4 (aux dac2 data out) alrclk abclk dsdata1 (tdm data in) empty empty empty empty dacl1 dacr1 dacl2 dacr2 dacl3 dacr3 dacl4 dacr4 auxl1 auxr1 auxl2 auxr2 8 on-chip dac channels auxiliary dac channels appear at aux dac ports unused slots asdata1 (tdm data out) adcl1 adcr1 adcl2 adcr2 auxl1 auxr1 auxl2 aux r2 unused unused unused unused unused unused unused unused 4 on-chip adc channels auxiliary adc channels unused slots 0 7414-018 figure 21. combined tdm/aux mo de dac and adc configuration
ad1937 rev. 0 | page 23 of 36 daisy-chain mode the ad1937 also allows a daisy-chain configuration to expand the system to 16 dacs and 8 adcs (see figure 22 to figure 26 ). in this mode, the dbclk frequency is 512 f s . the first eight slots of the tdm dac data stream belong to the first ad1937 in the chain and the last eight slots belong to the second ad1937. the second ad1937 is the device attached to the dsp tdm port. to accommodate 16 channels at a 96 khz sample rate, the ad1937 can be configured into a dual-line, tdm mode as shown in figure 23 . this mode allows a slower dbclk than normally required by the one-line tdm mode. the first four channels of each tdm input belong to the first ad1937 in the chain and the last four channels belong to the second ad1937. the dual-line tdm mode can also be used to send data at a 192 khz sample rate into the ad1937, as shown in figure 24 . there are two configurations for the adc port to work in daisy-chain mode. the first configuration is with an abclk at 256 f s , see figure 25 . the second configuration is with an abclk at 512 f s , see figure 26 . note that in the 512 f s abclk mode, the adc channels occupy the first eight slots; the second eight slots are empty. the tdm adc data in (asdata2) port of the first ad1937 must be grounded in all modes of operation. the i/o pins of the serial ports are defined according to the serial mode selected. see tabl e 19 for a detailed description of the function of each pin. see figure 27 for a typical ad1937 configuration with two external stereo dacs and two external stereo adcs. dlrclk dbclk 8 dac channels of the first ic in the chain 8 unused slots 8 dac channels of the second ic in the chain msb dsdata1 (tdm adc data in) of the second ad1937 dsdata2 (tdm dac data out) of the second ad1937; this is the tdm to the first ad1937 dac1l dac1r dac2l dac2r dac3l dac3r dac4l dac4r dac1l dac1r dac2l dac2r dac3l dac3r dac4l dac4r dac1l dac1r dac2l dac2r dac3l dac3r dac4l dac4r 32 bits dsp second ad1937 first ad1937 07414-019 figure 22. single-line daisy-chain tdm mo de 16-channel 48 kh z dac configuration dlrclk dbclk 8 dac channels of the second ic in the chain 8 dac channels of the first ic in the chain dsdata1 (tdm dac data in) dac1l dac1r dac2l dac2r dac1l dac1r dac2l dac2r dsdata3 (tdm dac2 data in) dac3l dac3r dac4l dac4r dac3l dac3r dac4l dac4r dsdata2 (tdm dac data out) dac1l dac1r dac2l dac2r dsdata4 (tdm dac2 data out) dac3l dac3r dac4l dac4r 32 bits dsp second ad1937 first ad1937 msb 07414-020 figure 23. dual-line daisy-chain tdm mode16-channel 96 khz dac configuration
ad1937 rev. 0 | page 24 of 36 dlrclk dbclk dsdata1 dac1l dac1r dac2l dac2r dsdata2 dac3l dac3r dac4l dac4l 32 bits msb 07414-021 figure 24. dual-line daisy-chain tdm mo de 8-channel 192 kh z dac configuration alrclk abclk asdata2 (tdm adc data in) of the second ad1937 in the chain adc1l adc1r adc2l adc2r 4 adc channels of first ic in the chain 4 adc channels of second ic in the chain a sdata1 (tdm adc data out) of the second ad1937 in the chain adc1l adc1r adc2l adc2r adc1l adc1r adc2l adc2r 32 bits msb dsp second ad1937 first ad1937 07414-022 figure 25. single-line daisy-chain tdm mode 256 f s adc configuration alrclk abclk 4 adc channels of second ic in the chain 4 adc channels of first ic in the chain adcl1 adcr1 adcl2 adcr2 adcl1 adcr1 adcl2 adcr2 a sdata1 (tdm adc data out) of the second ad1937 in the chain adcl1 adcr1 adcl2 adcr2 asdata2 (tdm adc data in) of the second ad1937 in the chain 32 bits msb dsp second ad1937 first ad1937 07414-023 figure 26. single-line daisy-chain tdm mode 512 f s adc configuration
ad1937 rev. 0 | page 25 of 36 table 19. pin function changes in tdm and tdm/aux modes (replication of table 18 ) mnemonic stereo modes tdm modes tdm/aux modes asdata1 adc1 data out tdm adc data out tdm data out asdata2 adc2 data out tdm adc data in aux dac1 data out (to external dac1) dsdata1 dac1 data in tdm dac data in tdm data in dsdata2 dac2 data in tdm dac data out aux adc1 data in (from external adc1) dsdata3 dac3 data in tdm dac2 data in (dual-line mode) aux adc2 data in (from external adc2) dsdata4 dac4 data in tdm dac2 data out (dual-line mode) aux dac2 data out (to external dac2) alrclk adc lrclk in/out tdm adc frame sync in/out tdm frame sync in/out abclk adc bclk in/out tdm adc bclk in/out tdm bclk in/out dlrclk dac lrclk in/out tdm dac frame sync in/out aux lrclk in/out dbclk dac bclk in/out tdm dac bclk in/out aux bclk in/out aux adc 1 lrclk bclk data mclk aux adc 2 lrclk bclk data mclk aux dac 1 aux dac 2 lrclk bclk data mclk lrclk bclk data mclk 30mhz 12.288mhz sharc is running in slave mode (interrupt-driven) sharc ad1937 tdm master aux master fsync-tdm (rfs) rxclk rxdata txclk txdata tfs (nc) asdata2 dsdata4 dbclk dlrclk dsdata2 dsdata3 mclki/mclkxi asdata1 alrclk abclk dsdata1 07414-027 figure 27. example of tdm/aux mode connection to sharc? (ad1937 as tdm master/aux master shown)
ad1937 rev. 0 | page 26 of 36 additional modes the ad1937 offers several additional modes for board level design enhancements. to reduce the emi in board level design, serial data can be transmitted without an explicit bclk. see figure 28 and figure 29 for an example of a dac tdm data transmission mode that does not require high speed dbclk. this configuration is applicable when the ad1937 master clock is generated by the pll with the dlrclk as the pll reference frequency. to relax the requirement for the setup time of the ad1937 in cases of high speed tdm data transmission, the ad1937 can latch in the data using the falling edge of dbclk. this effec- tively dedicates the entire bclk period to the setup time. this mode is useful in cases where the source has a large delay time in the serial data driver. figure 30 shows this pipeline mode of data transmission. both the bclk-less and pipeline modes are available on the adc serial data port. dlrclk internal dbclk dsdatax 32 bits 07414-028 figure 28. serial dac data transmission in tdm format without dbclk; 2-channel 64 bclks per frame mode (applicable only if pll locks to dlrclk; this mode is also available in the adc serial data port) dlrclk dbclk dsdatan data must be valid at this bclk edge msb 0 7414-029 figure 29. serial dac data transmission in tdm format without dbclk; 128 to 512 bclks per frame tdm mode (applicable only if pll locks to dlrclk; this mode is also available in the adc serial data port) dlrclk internal dbclk t dm dsdatan 07414-128 figure 30. i 2 s pipeline mode in dac serial data transmission (applicable in stereo and tdm, useful for high frequency tdm transmission; this mode is also available in the adc serial data port)
ad1937 rev. 0 | page 27 of 36 control registers definitions the global address for the ad1937 is 0x08 ored with addr1 and addr0 and one r/ w bit; see and . the address bits (bits[18:17]) setting must correspond to the low/high state of pin 30 and pin 35. all registers are reset to 0, except for the dac volume registers that are set to full volume. figure 13 figure 14 note that the first setting in each control register parameter is the default setting. table 20. register format global address r/ w register address data bit 23:17 16 15:8 7:0 table 21. register addresses and functions hexadecimal address function 0x00 0 pll and clock control 0 0x01 1 pll and clock control 1 0x02 2 dac control 0 0x03 3 dac control 1 0x04 4 dac control 2 0x05 5 dac individual channel mutes 0x06 6 dac1l volume control 0x07 7 dac1r volume control 0x08 8 dac2l volume control 0x09 9 dac2r volume control 0x0a 10 dac3l volume control 0x0b 11 dac3r volume control 0x0c 12 dac4l volume control 0x0d 13 dac4r volume control 0x0e 14 adc control 0 0x0f 15 adc control 1 0x10 16 adc control 2 pll and clock control registers table 22. pll and clock control 0 register (address 0, 0x00) bit value function description 0 0 normal operation pll power-down 1 power-down 2:1 00 input 256 ( 44.1 khz or 48 khz) mclki/mclkxi pin functionality (pll active), master clock rate setting 01 input 384 ( 44.1 khz or 48 khz) 10 input 512 ( 44.1 khz or 48 khz) 11 input 768 ( 44.1 khz or 48 khz) 4:3 00 xtal oscillator enabled mclko/mclkxo pin, master clock rate setting 01 256 f s vco output 10 512 f s vco output 11 off 6:5 00 mclki/mclkxi pll input 01 dlrclk 10 alrclk 11 reserved 7 0 disable: adc and dac idle internal master clock enable 1 enable: adc and dac active
ad1937 rev. 0 | page 28 of 36 table 23. pll and clock control 1 register (address 1, 0x01) bit value function description 0 0 pll clock dac clock source select 1 mclk 1 0 pll clock adc clock source select 1 mclk 2 0 enabled on-chip voltage reference 1 disabled 3 0 not locked pll lock indicator (read-only) 1 locked 7:4 0000 reserved dac control registers table 24. dac control 0 register (address 2, 0x02) bit value function description 0 0 normal power-down 1 power-down 2:1 00 32 khz/44.1 khz/48 khz sample rate 01 64 khz/88.2 khz/96 khz 10 128 khz/176.4 khz/192 khz 11 reserved 5:3 000 1 cycle (i 2 s mode) dsdata delay (bclk periods) 001 0 (left-justified mode) 010 8 cycles (right-justified 24-bit mode) 011 12 cycles (right-justified 20-bit mode) 100 16 cycles (right-justified 16-bit mode) 101 reserved 110 reserved 111 reserved 7:6 00 stereo (normal) serial format 01 tdm single-line, standalone, and daisy-chain modes 10 tdm/aux mode (adc-, dac-, tdm-coupled) 11 tdm dual-line daisy-chain mode
ad1937 rev. 0 | page 29 of 36 table 25. dac control 1 register (address 3, 0x03) bit value function description 0 0 latch in midcycle (normal) dbclk active edge (tdm_in) 1 latch in at end of cycle (pipeline) 2:1 00 64 (2 channels) dbclks per frame 01 128 (4 channels) 10 256 (8 channels) 11 512 (16 channels) 3 0 left low dlrclk polarity 1 left high 4 0 slave dlrclk master/slave 1 master 5 0 slave dbclk master/slave 1 master 6 0 dbclk pin dbclk source 1 internally generated 7 0 normal dbclk polarity 1 inverted table 26. dac control 2 register (address 4, 0x04) bit value function description 0 0 unmute master mute 1 mute 2:1 00 flat de-emphasis (32 khz/44.1 khz/48 khz mode only) 01 48 khz curve 10 44.1 khz curve 11 32 khz curve 4:3 00 24 bits word width 01 20 bits 10 reserved 11 16 bits 5 0 noninverted dac output polarity 1 inverted 7:6 00 reserved table 27. dac individual channel mutes register (address 5, 0x05) bit value function description 0 0 unmute dac1l mute 1 mute 1 0 unmute dac1r mute 1 mute 2 0 unmute dac2l mute 1 mute 3 0 unmute dac2r mute 1 mute 4 0 unmute dac3l mute 1 mute 5 0 unmute dac3r mute 1 mute 6 0 unmute dac4l mute 1 mute 7 0 unmute dac4r mute 1 mute
ad1937 rev. 0 | page 30 of 36 table 28. dacxx volume controls register s (address 6 to address 13, 0x06 to 0x0d) bit value function description 7:0 0 no attenuation dac volume control 1 to 254 ?0.375 db per step 255 full attenuation adc control registers table 29. adc control 0 register (address 14, 0x0e) bit value function description 0 0 normal power-down 1 power down 1 0 off high-pass filter 1 on 2 0 unmute adc1l mute 1 mute 3 0 unmute adc1r mute 1 mute 4 0 unmute adc2l mute 1 mute 5 0 unmute adc2r mute 1 mute 7:6 00 32 khz/44.1 khz/48 khz output sample rate 01 64 khz/88.2 khz/96 khz 10 128 khz/176.4 khz/192 khz 11 reserved table 30. adc control 1 register (address 15, 0x0f) bit value function description 1:0 00 24 bits word width 01 20 bits 10 reserved 11 16 bits 4:2 000 1 cycle (i 2 s mode) asdata delay (bclk periods) 001 0 (left-justified mode) 010 8 cycles (right-justified 24-bit mode) 011 12 cycles (right-justified 20-bit mode) 100 16 cycles (right-justified 16-bit mode) 101 reserved 110 reserved 111 reserved 6:5 00 stereo serial format 01 tdm single-line, standalone, and daisy-chain modes 10 tdm/aux mode (adc-, dac-, tdm-coupled) 11 reserved 7 0 latch in midcycle (normal) abclk active edge (tdm_in) 1 latch in at end of cycle (pipeline)
ad1937 rev. 0 | page 31 of 36 table 31. adc control 2 register (address 16, 0x10) bit value function description 0 0 50/50 (allows 32, 24, 20, or 16 bclks per channel) alrclk format 1 pulse (32 bclks per channel) 1 0 drive out on falling edge (def) abclk polarity 1 drive out on rising edge 2 0 left low alrclk polarity 1 left high 3 0 slave alrclk master/slave 1 master 5:4 00 64 cycles abclks per frame 01 128 cycles 10 256 cycles 11 512 cycles 6 0 slave abclk master/slave 1 master 7 0 abclk pin abclk source 1 internally generated
ad1937 rev. 0 | page 32 of 36 applications circuits typical application circuits are shown in figure 31 through figure 34 . figure 31 shows a typical adc input filter circuit. recommended loop filters for lrclk and mclk as the pll reference are shown in figure 32 . output filters for the dac outputs are shown in figure 33 and a regulator circuit is shown in figure 34 . 2 1 3 op275 ? + 6 7 5 op275 ? + 5.76k ? 5.76k ? 237 ? 5.76k ? 120pf 600z a udio input 100pf 5.76k ? 120pf 4.7f + 237 ? 4.7f + 100pf 1nf npo 1nf npo adcxxn adcxxp 07414-030 figure 31. typical adc input filter circuit 39nf 2.2nf lf lrcl k a vdd2 3.32k ? 5.6nf 390pf lf mclk avdd2 562? 07414-031 figure 32. recommended loop filters for lrclk or mclk as pll reference 2 1 3 op275 ? + 2.2nf npo audio output 604? 68pf npo 150pf npo 560pf npo 270pf npo dac outn 3.01k ? 11k? dac outp 1.50k ? 5.62k ? 11k? 5.62k ? 07414-032 figure 33. typical dac output filter circuit (differential) 10f + e c b vsupply 5v vsense 3.3v fzt953 vdrive 1k? 100nf 10f + 100nf 07414-033 figure 34. recommended 3.3 v regulator circuit
ad1937 rev. 0 | page 33 of 36 outline dimensions compliant to jedec standards ms-026-bcd 051706-a top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 11.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 0.15 0.05 7 3.5 0 figure 35. 64-lead low profile quad flat package [lqfp] (st-64-2) dimensions shown in millimeters ordering guide model temperature range packag e description package option ad1937wbstz 1 C40c to +125c 64-lead lqfp st-64-2 ad1937wbstz-rl 1 C40c to +125c 64-lead lqfp, 13 tape and reel st-64-2 EVAL-AD1937EBZ 1 evaluation board 1 z = rohs compliant part.
ad1937 rev. 0 | page 34 of 36 notes
ad1937 rev. 0 | page 35 of 36 notes
ad1937 rev. 0 | page 36 of 36 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07414-0-9/08(0)

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